This invention relates to a semiconductor memory device and, in particular, to a semiconductor memory device having a plurality of programmable and erasable non-volatile memory cells.
A conventional semiconductor memory device of the type described includes a non-volatile semiconductor memory device which has a plurality of programmable and erasable non-volatile memory cells. Such each non-volatile memory cell has a double gate structure which is formed by a control gate and a floating gate.
Further, the non-volatile semiconductor memory device may be classified into a flash memory wherein a plurality of memory cells are erased once and an EEPROM wherein each of memory cells is selectively erased.
In addition, various kinds of memory cells have been proposed one of which utilizes Fowler-Nordheim (F-N) tunneling phenomenon during erasing and writing operations and another of which utilizes the F-N tunneling phenomenon during the erasing operation and injection of hot electrons into the floating gate during the writing operation.
It is common to any one of the non-volatile semiconductor devices mentioned above that a threshold value of the memory cell is changed from one to another during the erasing operation and the writing operation.
At any rate, each memory cell has a source, a drain and a double gate structure as described above. In this case, voltages which are given to the source, the drain and the control gate in a reading operation are different from those in the erasing operation and the writing operation. This is because the threshold values of the memory cell should be changed during the erasing and the writing operations, as mentioned before. Therefore, a voltage control circuit is normally included in the non-volatile semiconductor device.
Subsequently, description will be made in detail about the writing and erasing operations of the memory cell. In this event, the writing operation is carried out by injecting the hot electrons from the drain into the floating gate, while the erasing operation is made by the use of the F-N tunneling phenomenon.
More particularly, the writing operation is carried out by giving a high voltage of about 12V and a voltage of 6V to the control gate and the drain, respectively. Under the circumstances, the source is grounded and thereby, the hot electrons which are generated between the drain and the source are injected into the floating gate from an edge of the drain. Such injection of the hot electrons raises the threshold value.
On the other hand, the erasing operation is carried out by giving a high voltage of 12V to the source on the condition that the control gate and the drain are grounded and opened, respectively. Alternatively, a negative high voltage may be given to the control gate during the erasing operation on the condition that the drain and the source are opened and supplied with a voltage of 5V, respectively. In either one of the above mentioned cases, a high electric field is generated between the floating gate and the source. The electrons injected into the floating gate are drawn from an edge of the source by the F-N tunneling phenomenon. As a result, the threshold value of the memory cell is reduced.
Thus, desired voltages are inevitably applied to the drain, the source, and the control gate from the above voltage control circuit during the writing and erasing operations.
Recently, the number of the memory cells in the flash memory is increased with an increase of a memory capacity in the semiconductor memory device. In this case, proposal has been made about a flash memory in which the memory cells are divided into a desired number of blocks (namely, memory arrays). With such a structure, the erasing operation can be carried out at every one of the blocks.
In such a flash memory, a plurality of blocks are arranged in a desired direction. The sources of the memory cells in each block are commonly connected to each of source switches for selectively supplying an erasing voltage for each block. The source switches are connected to a power supply pad for supplying the erasing voltage via an erasing voltage supply line.
With such a structure, as the blocks are increased in number, the length of each erasing voltage supply line between the power supply pad and each source switch becomes long. In this case, the erasing voltage supply line has a distribution resistance dependent on a wiring width and a wiring thickness. This shows that the distribution resistance is minimum when the block is closest to the power supply pad. On the other hand, the distribution resistance is maximum when the block is farthest from the power supply pad.
In this structure, let an erasing voltage of a pulse shape be supplied from the power supply pad to the respective blocks. In this case, a highest voltage is given to the closest block, while a lower voltage is given to a farther block from the power supply pad. Thus, fluctuation of the erasing voltage in each block takes place and results in a difference among the threshold values in the blocks after the memory cells are erased in the blocks. Thereby, an operating margin is reduced on a minimum value side of a power supply voltage in the flash memory.
To solve such a problem, Japanese Unexamined Patent Publication No. H6-325584 (hereinafter, called a reference) discloses that a smoothing resistance is connected in accordance with a position of each block between the source switch and a branch point of the erasing voltage supply line. In this case, a larger smoothing resistance is connected to the block closer to the power supply pad, while a lower smoothing resistance is connected to the block farther from the power supply pad. Thus, resistance values of a path from the power supply pad to the source switch via the erasing voltage supply line and the smoothing resistance are equalized to one another and the number of the erasing pulses is also adjusted during the erasing operation. With this structure, it is possible to adjust the difference of erasing voltage levels given to each block via the source switch by adjusting with the number of the erasing pulses. As a result, the fluctuation of the threshold levels in each block cells can be reduced after erasing the memory.
In the reference, an attention is directed to only reduction of the fluctuation of the threshold value after erasing the memory cell. However, no attention is paid for a variation of a ground potential of the source that might occur in each memory cell during the writing operation. Further, no suggestion is made about an influence due to the variation of the ground potential in the reference.
Further, if the smoothing resistances are connected to each block like in the reference, the number of the resistances is increased with an increase of the block number. Therefore, the equalization of the erasing voltage due to the resistances brings about an increase of both a chip size and a power consumption. Further, it is difficult from a viewpoint of a design to provide the smoothing resistances having the different resistance values for the respective blocks like in the reference.